A wide variety of sample and hold (S/H) circuits have been developed for use in electronic systems. S/H circuits have two modes of operation--a sample mode during which the S/H circuit tracks the voltage applied to its input; and, a hold mode during which the S/H circuit stores the input voltage that occurred immediately proceeding the time the S/H circuit is switched from its sample mode to its hold mode of operation.
One of the major disadvantages of prior art S/H circuits is that the output produced during the hold mode of operation includes an offset voltage error. The offset voltage error occurs because prior art S/H circuits generally do not connect in circuit both of the operational amplifiers included in such circuits during both the sample mode of operation and the hold mode of operation. More specifically, the main elements of a typical prior art sample and hold circuit include a pair of operational amplifiers, a storage capacitor, electronic switches and one or more resistors. The electronic switches are positioned in the circuit such that during the sample mode of operation, both of the operational amplifiers are connected in circuit. Usually one of the operational amplifiers applies the input voltage to the capacitor and the other operational amplifier senses the voltage on the capacitor and produces a feedback signal that is applied to the first operational amplifier. During the hold mode of operation, the second operational amplifier senses the voltage on the capacitor and produces an output signal. The first operational amplifier is not connected in circuit. The end result of this arrangement is that the output voltage produced during the hold mode of operation includes an offset voltage produced by the first operational amplifier, said offset voltage creating an error in the output voltage. Obviously errors in signals are undesirable. Thus, there is a need for a sample and hold circuit that eliminates this source of error. That is, there is a need for a sample and hold circuit that has substantially zero offset voltage error.
Therefore, it is an object of this invention to provide a new and improved sample and hold circuit.
It is another object of this invention to provide a sample and hold circuit that has essentially zero offset voltage error in its output.
It is a still further object of this invention to provide a relatively uncomplicated sample and hold circuit that has essentially zero offset voltage error in the output signal produced by the circuit during the hold mode of operation.
Another disadvantage of prior art sample and hold circuits is the error that occurs in the output signal as a result of the storage capacitor leaking charge and as a result of the current drawn from the capacitor by the operational amplfier producing the output voltage during the hold mode of operation. Such errors become of particular significance when the sample and hold circuit is placed in the hold mode of operation for a relatively long period of time, because these effects are cumulative.
Therefore, it is a further object of this invention to provide a sample and hold circuit wherein the effect of capacitor charge leakage is reduced.
It is yet another object of this invention to provide a sample and hold circuit wherein the effect on the output voltage of the S/H circuit caused by the output operational amplifier drawing current from the capacitor during the hold mode of operation is reduced.